Modern electronic devices, such as microprocessors, often include a complex matrix of logic gates arranged to perform particular tasks and functions. These logic gates are often interconnected in two parallel arrangements, one arrangement for operation, and another arrangement for testing the functionality of the circuit. Linking a plurality of latches together into a “scan chain” is one popular method of arranging logic units for functional/operational testing. One skilled in the art will appreciate that there are a wide variety of ways to arrange circuit components to facilitate testing. As used herein, “scan chain” refers generally to an arrangement of logic units coupled together for testing.
There are also a number of popular methods to generate test data to apply to the scan chains, as will be understood to one skilled in the art. Generally, test data is data designed to test a particular function or functional unit of an electronic circuit. In scan testing, n scan chains, for example, are loaded with one n-bit block of data at a time each clock cycle (i.e., one “bit-slice” of the scan chain is loaded at a time). Given the test set, the set of n-bit blocks (i.e., bit-slices of the scan chain) can be obtained.
Test data compression provides a means to reduce test costs by reducing tester storage, test time, and test data bandwidth requirements. Compressing the output response is relatively easy because lossy compression techniques can be employed, e.g., using multiple input signature registers (MISR). However, compressing test vectors is much more difficult because lossless compression techniques must be used.
Modern systems have employed a number of coding techniques for test cubes. These include run-length codes, selective Huffman codes, Golomb codes, frequency directed codes, VIHC codes, LZ77, Mutation codes, packet-based codes, and non-linear combination codes. A special class of test vector compression schemes involves using a linear decompressor which uses only linear operations to decompress the test vectors. This class of schemes includes techniques based on linear feedback shift register (LFSR) reseeding and combinational linear expansion circuits consisting of exclusive-OR (XOR) gates. Linear compression schemes are very efficient at exploiting “don't care” values in the test cubes to achieve large amounts of compression. Typical current commercial tools for compressing test vectors rely on linear compression schemes.
The amount of compression that can be achieved with linear compression schemes depends directly on the number of specified bits in the test cubes. While linear decompressors are very efficient at exploiting don't cares in the test set, they cannot exploit correlations in the test data, and hence they cannot compress the test data to less than the total number of specified bits in the test data.
Because of problems with linear compression, some systems use certain non-linear coding techniques. For example, in [Krishna 02] (“Krishna”), supplies inputs to a linear decompressor that are encoded using a non-linear code. Specifically, the objective in Krishna was to select the seeds for the LFSR in such a way that they could be effectively compressed by a non-linear code. The Krishna approach, however, only applies in LFSR reseeding, and is only effective whenever the seed is (periodically) loaded. [Sun 04] (“Sun”) takes another approach, wherein dictionary coding and LFSR reseeding are combined such that either one or the other is used to load each scan bit-slice. The Sun approach, however, does not support statistical encoding combined with a continuous-flow linear decompression with greater efficiency.
Therefore, there is a need for a test data compression/decompression system and/or method that that addresses at least some of the problems and disadvantages associated with conventional systems and methods.